Digital circuit technology has been developed to the point where it is practical to begin implementing digital signal processing in consumer electronic apparatus. For example, manufacturers are beginning to introduce television receivers and video cassette recorders which incorporate digital electronics to add special features such as freeze frame or picture-in-picture to the receivers. In order to accomplish digital processing it is first necessary to convert the received broadcast signal to digital format, and this function is performed by an analog-to-digital converter (ADC) In digital television signal processing it is desirable to sample the television signal at a rate of four times the color subcarrier frequency (about 14.32 MHz), and convert the signal to pulse code modulated (PCM) format with 8-bit resolution. Bipolar ADC's exist which operate satisfactorily at these rates and resolution; however, the technology of choice of performing digital processing in electronic products is metal-oxide-semiconductor (MOS) field effect transistor (FET) technology. The reason is that MOSFET technology permits dense packing of devices with low power dissipation.
Prior art 8-bit 14 MHz ADC's implemented in MOS technology are currently available; however production yields of such devices are relatively poor. An example of a typical MOS ADC is described in U.S. Pat. No. 4,691,189, which is incorporated herein by reference Numerous variants of this type of ADC have been designed to increase either its operating speed or its conversion linearity. However, these designs do not provide apparatus with satisfactory performance/yields for video rate signal processing. In the ADC's of the type illustrated in U.S. Pat. No. 4,691,189 performance is traded off against yield, in that the transistor sizes are made extremely small to increase packing density and thereby yield However, as transistor devices are made smaller, stray capacitances become increasingly more significant, which stray capacitances adversely affect circuit performance. In addition the stray capacitances in MOS circuitry tend to be non-linear with applied potential and therefore are not completely predictable.
The comparator circuitry described in U.S. Pat. No. 4,691,189, a portion of which is illustrated in FIG. 1 herein, utilizes two inverting amplifier stages 11, 12 which are capacitively coupled (C2) in cascade, and each of which includes switching circuitry (TG1, TG2) for autozeroing during a portion of each sample period. The coupling capacitance C2 inherently includes a stray capacitance between one of its plates and the circuit substrate, which stray capacitance is of the same order of magnitude as the coupling capacitance itself. This stray capacitance will slow the response time at the output of the first inverting amplifier and thereby slow the response time of the comparator.
In the comparator design of U.S. Pat. No. 4,691,189 the inverting amplifiers I1, I2 are designed with complementary FET's having a common gate connection and their drain-source conduction paths are serially coupled between supply potentials The autozeroing switches are arranged to connect the output terminals of the inverting amplifiers to their respective input terminals, immediately prior to each signal sampling interval. This form of autozeroing renders the inverting amplifiers sensitive to very slight changes of input potential (a desirable characteristic for this type of comparator).
For every comparator in the ADC, and there may be 256 comparators in an 8-bit flash ADC, at least all of the second inverting amplifiers I2 will exhibit a saturated output potential each sample period, requiring a significant potential change during autozero. It will be recognized that the speed at which the inverting amplifiers can autozero is adversely affected by the stray capacitance in the circuit, for example the stray capacitances between C1 and C2 and substrate and the stray capacitances between the autozero switching circuits (TG1, TG2) and substrate.
It is an object of this invention to provide an MOS comparator circuit with performance/yield characteristics suitable for video rate ADC circuitry.